Pll circuit

ABSTRACT

A PLL circuit comprises a phase comparator for comparing phases between a reference signal and an internal signal and outputting a phase difference signal according to a phase difference therebetween, a voltage controlled oscillator group composed of a plurality of oscillators which have mutually different frequency variable ranges and whose oscillation frequencies are respectively controlled in accordance with a phase control signal, a selecting means for selecting one of the outputs from the plurality of oscillators based on the phase difference signal or the phase control signal, and a frequency divider for generating the internal signal by dividing an output of an oscillator selected by the selecting means, and when the oscillator selecting state is changed, an output phase of the frequency divider is approximated to the phase of the reference signal. Thereby, a required voltage controlled oscillator can be selected in a short time according to a desirable oscillation frequency.

TECHNICAL FIELD

The present invention relates to a PLL (Phase Locked Loop) circuit withbuilt-in voltage controlled oscillators, and particularly, to a PLLcircuit which requires a wide oscillation frequency band.

BACKGROUND ART

With diversification in mobile communication systems in recent years,carrying out transmission and reception in various methods by use of asingle mobile communication terminal has been demanded, and meanwhile,normally, since different mobile communication systems employ differentfrequency bands, a transmitting and receiving function in multiplefrequency bands, a so-called multiband radio function has been requiredfor such a multi-mode terminal.

For a frequency synthesizer used in a multiband radio, it is necessaryto be capable of generating local signals in various frequency bandscorresponding to the multibands. For example, methods such as GSM(Global System for Mobile Communications) employing a 900 MHz band, DCS(Digital Cellular System) employing a 1800 MHz band, PCS (PersonalCommunication Services) employing a 1900 MHz band, and UMTS (UniversalMobile Telecommunication System) employing a 2 GHz band have been widelyutilized around the world, and development of a four-band radio whichcan be used for all these frequency bands has been demanded.

In the case of realizing a frequency synthesizer corresponding to such afour-band radio, it is necessary to prepare respective unit synthesizersfor GSM transmission, for GSM reception, for DCS transmission, for DCSreception, for PCS transmission, for PCS reception, for UMTStransmission, and for UMTS reception. Since the reception frequency ofPCS and transmission frequency of UMTS are almost identical in theirbands, both can be used by a single synthesizer, however, this is merelya special case, and basically, unit synthesizers in a numberrespectively corresponding to necessary multiple frequencies areprepared. Accordingly, if the number of bands increases, the number ofunit synthesizers increases in proportion thereto, and hardware resultson a huge scale.

As a method for solving such problems, a method of improving anoscillator in modulation sensitivity so as to expand a variable range ofthe oscillator itself can be considered, however, in this case, there isa problem of fluctuation in frequency of a local oscillator owing tonoise and the like from the outside and inside of the chip.

In addition, there is a construction to generate signals having aplurality of frequency bands greater in the number of unit synthesizersby a small-scale circuit configuration provided by combining anarithmetic circuit composed of a frequency divider and a mixer formultiplication with two unit synthesizers. However, this cannotcorrespond to all the combining communication methods, and there is adrawback in that the number of synthesizers is consequently increased.

Therefore, a method for selecting a voltage controlled oscillator by anexternal signal according to a desirable oscillation frequency to beobtained has been suggested by use of a plurality of voltage controlledoscillators having different controlled voltage-oscillation frequencycharacteristics.

In this method, since the plurality of voltage controlled oscillatorstake charge of mutually different frequency ranges, the frequency rangeas a whole being wide, although each voltage controlled oscillator has anarrow frequency variable range. Since each voltage controlledoscillator has a narrow frequency variable, each voltage controlledoscillator can take a small modulation sensitivity, which makes itpossible to stably operate synthesizers.

FIG. 10 is a diagram showing a configuration example of a quadruplecircuit to select from a plurality of voltage controlled oscillators byan external signal and generate a clock.

The present conventional art is, as shown in FIG. 10, a quadruplecircuit composed of a PLL circuit having a phase comparator 1, a chargepump 2, a loop filter 3, a voltage controlled oscillator group 4consisting of four voltage controlled oscillators having differentcontrol voltage-oscillation frequency characteristics, a selectioncircuit 6, a frequency divider 5, an N-channel MOS transistor NM5, and aresistor R. When an output signal S14 from the selection circuit 6 ishigh in potential (H), the N-channel MOS transistor NM5 is turned on,and by a series connection circuit composed of the resistor R and MOStransistor NM5, current of an output signal S4 from the loop filter 3 isextracted, and potential of a signal S4 line is set to a voltage withina range between reference voltages Vref1 and Vref2, which will bedescribed later (see Japanese Published Unexamined Patent ApplicationNo. H09-214335.)

In the following, operations of a quadruple circuit constructed asdescribed above will be described.

The phase comparator 1 generates output signals S1 and S2 based onresults of a comparison between a reference signal CK1 and an internalsignal CK2. The signal S1 is a signal to indicate a phase lead amount ofthe reference signal CK1 over the internal signal CK2, the signal S2 isa signal to show a phase lead amount of the internal signal CK2 over thereference signal CK1, and these signals S1 and S2 are inputted into thecharge pump 2.

An output signal S3 from the charge pump 2 is inputted into the loopfilter 3 and is, after a high-frequency component is removed by the loopfilter 3, inputted into the voltage controlled oscillator group 4 as acontrol voltage S4 of the voltage controlled oscillator group 4.

In the voltage controlled oscillator group 4, signals S10 to S13generated in the selection circuit 6 are inputted so that one voltagecontrolled oscillator is selected from the four voltage controlledoscillators of the voltage controlled oscillator group 4. An outputsignal CK3 from the voltage controlled oscillator group 4 is dividedinto four by the voltage divider 5 to become an internal signal CK2.

In the conventional art, the circuit locks when operation is performedso that the signal CK1 and signal CK2 coincide in frequency and phase,and a frequency of the signal CK3 obtained from the voltage controlledoscillator group 4 becomes quadruple that of the reference signal CK1.

FIG. 11 is a block diagram showing a configuration of the selectioncircuit 6 shown in FIG. 10.

When the output signals S10 to S13 from the selection circuit 6 arechanged, the output signal S14 becomes high in potential (H) for a fixedtime, and thereby, potential of the signal S4 is set so as to be in arange of threshold voltages Vref1 and Vref2 (Vref2>Vref1).

In the selection circuit 6, a voltage comparator 418 having a thresholdvoltage Vref1 and a voltage comparator 419 having a threshold voltageVref2 are provided. In the voltage comparator 418, an output signal S15is set to a high potential (H) when voltage of the inputted controlsignal S4 is lower than the threshold voltage Vref1, and an outputsignal S15 is set to a low potential (L) when voltage of the controlsignal S4 is higher than the threshold voltage Vref1. In addition, inthe voltage comparator 419, an output signal S16 is set to a highpotential (H) when voltage of the inputted control signal S4 is lowerthan the threshold voltage Vref2, and an output signal S16 is set to alow voltage (L) when voltage of the control signal S4 is higher than thethreshold voltage Vref2.

In addition, a NOR gate 420 for setting a signal S17 to a high potential(H) when the signals S15 and S16 are both low in potential (L) and for,in other cases, setting the same to a low potential (L), an AND gate 421for setting a signal S18 to a high potential (H) when the signals S15and S16 are both high in potential (H) and for, in other cases, settingthe same to a low potential (L), 2-bit up counters 422 and 423, asubtractor 424 for subtracting an output count value S20 of the counter423 from an output count value S19 of the counter 422, and a decoder 425for setting any of only one of the output signals S10 to S13 to a highpotential (H) in accordance with a count value S21 inputted from thesubtractor 424 are provided.

By the selection circuit 6 having such operation characteristics, fromthe four voltage controlled oscillators having different controlvoltage-oscillation frequency characteristics, one voltage controlledoscillator according to a quadruple frequency of the frequency of thereference signal CK1 is automatically selected.

Furthermore, when the selecting state is changed by the selectioncircuit 6, the signal S14 is temporarily made high in potential (H), andpotential of the signal S4 is forcibly set to a value higher than athreshold voltage Vref1 shown in FIG. 12 and also lower than a thresholdvalue Vref2, therefore, outputs from the NOR gate 420 and AND gate 421are once returned to a low potential (L), whereby in the selecting stateof the voltage controlled oscillator group 4 having different controlvoltage-oscillation frequency characteristics, malfunction can beprevented.

FIG. 12 is a characteristics diagram showing oscillation frequencycharacteristics, with respect to a voltage of the control signal S4, ofthe voltage controlled oscillator group 4 shown in FIG. 10. Here,frequencies f1 to f8 have a relationship of f1<f2<f3<f4<f5<f6<f7<f8.

First, description will be given for a case where a desirableoscillation frequency, namely, a quadruple frequency fosc of a frequencyof the reference signal CK1 to be inputted into the phase comparator 1is f1<fosc<f2.

When a lock occurs only at a characteristic D shown in FIG. 12, namely,when voltage of the control signal S4 is not deviated from the rangebetween the threshold voltage Vref1 and threshold voltage Vref2, theoutput signals S17 and S18 from the NOR gate 420 and AND gate 421 neverbecome high in potential (H), therefore, the counters 422 and 423 neverperform a counting operation, and the condition of the output signalsS10 to S13 does not change from their initial condition.

In addition, when the characteristic shifts to a characteristic C shownin FIG. 12, further shifts to a characteristic B, and the circuit isfinally locked, operations are as follows.

When the control voltage S4 exceeds the threshold voltage Vref2 at thecharacteristic D, the output signal S17 from the NOR gate 420 becomeshigh in potential (H), the output value S19 from the counter 422 and anoutput value S21 from the subtractor 424 are increased by one, whereby,in the decoder 425, only the output signal S13 is switched over from ahigh-potential (H) condition to a low-potential (L) condition, also onlythe output signal S12 is switched over from a low-potential (L)condition to a high-potential state (H) condition, and thecharacteristic shifts to the characteristic C.

At this time of switching over, since the signal S14 temporarily becomeshigh in potential (H) and the control signal S4 temporarily returns to avoltage in the range between the threshold voltage Vref1 and thresholdvoltage Vref2, the output signal S17 from the NOR gate 420 changes froma high potential (H) to a low potential (L).

Even after PLL control according to the characteristic C is performed assuch, since frequency of the internal signal is still lower than thequadruple frequency of the reference signal, the control voltage S4again exceeds the threshold voltage Vref2, the selection circuit 6repeats the aforementioned operations, and the characteristic shifts tothe characteristic B. At this point in time, from the voltage controlledoscillator group 4, a frequency roughly the same as that of thereference signal CK1 is being outputted, however, since the phase of thefrequency divider 5 does not change in a short time, the phasecomparator 1 still operates so as to set the frequency of the internalsignal high, and consequently, the control voltage S4 again exceeds thethreshold value Vref2, the selection circuit 6 repeats theaforementioned operations, and the characteristic shifts to acharacteristic A.

As a result, frequency of the voltage controlled oscillator group 4becomes higher than that of the reference signal, the phase of thefrequency divider 5 has a lead over that of the reference signal,therefore, the control voltage S4 falls below the threshold voltageVref1, and the characteristic is again shifted to the characteristic Bby the selection circuit 6.

Thereafter, the two frequencies are equalized, and a lock finally occursat the characteristic B.

However, as mentioned above, in a case where a voltage controlledoscillator is selected according to a desirable oscillation frequency byuse of a plurality of voltage controlled oscillators having differentcontrol voltage-oscillation frequency characteristics, although abroadband PLL circuit can be realized, since, even when a preferredvoltage controlled oscillator is selected, the phase of the frequencydoes not change in a short time, an output from the phase comparatordoes not sufficiently follow a change in frequency, and consequently, aconsiderably long time is spent before an optimal oscillator isselected, therein a problem exists.

Since the phase is integration of the frequency, even if an optimaloscillator is selected and an internal signal having a frequencyidentical to that of the reference signal is inputted into the phasecomparator, it takes a great deal of time to bring about an output fromthe phase comparator into a locked condition, and the output is notimmediately brought into a locked condition.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a PLL circuit capableof selecting a required voltage controlled oscillator according to adesirable oscillation frequency in a short time by use of a plurality ofvoltage controlled oscillators having different controlvoltage-oscillation frequency characteristics.

In order to achieve the above-described object, a PLL circuit accordingto the present invention comprises: a phase comparing means forcomparing phases between a reference signal and an internal signal andoutputting a phase difference signal according to a phase differencetherebetween; a plurality of oscillators which have mutually differentfrequency variable ranges and whose oscillation frequencies arerespectively controlled in accordance with a phase difference signal; aselecting means for selecting one of the outputs from the plurality ofoscillators based on the phase difference signal; and a frequencydividing means for generating the internal signal by dividing an outputof the oscillator selected by the selecting means, wherein provided is ameans for approximating, when the oscillator selecting state is changed,an output phase of the frequency dividing means to the phase of thereference signal.

In addition, the plurality of oscillators have mutually overlappingfrequency variable ranges.

Furthermore, the plurality of oscillators have mutually differentoperating frequency ranges.

Still furthermore, the selecting means switches over outputs from theplurality of oscillators based on a history of the phase differencesignal or the phase control signal.

Still furthermore, the oscillators are voltage controlled oscillators,and provided is a means for converting the phase difference signal to anoscillator control voltage.

In addition, provided is a means for setting two threshold voltageshaving mutually different values within a variable voltage range of thecontrol voltage of the voltage controlled oscillator and temporarilysetting, when the voltage controlled oscillator selecting state ischanged, a value of the oscillator control voltage in a range betweenthe two threshold voltages.

In addition, provided is a means for changing a value of the temporarilysetting the oscillator control voltage in accordance with a history whenthe voltage controlled oscillator selecting state is changed.

In addition, when the voltage controlled oscillator selecting state isswitched over as a result of the oscillator control voltage becoming outof the range between the two threshold voltages, the temporarily settingoscillator control voltage is set, out of the two threshold voltages, inthe vicinity of the oscillator control voltage-side threshold voltage.

In addition, when the voltage controlled oscillator selecting state isswitched over as a result of the oscillator control voltage becoming outof the range between the two threshold voltages and when the oscillatorcontrol voltage becomes out of the range between the two thresholdvoltages twice or more in series, the temporarily setting oscillatorcontrol voltage is set, out of the two threshold voltages, in thevicinity of the oscillator control voltage-side threshold voltage.

In addition, when the oscillator control voltage becomes out of therange between the two threshold voltages, depending on whether thisoscillator control voltage is greater than the two threshold voltages orsmaller than the two threshold voltages, whether setting the oscillatorcontrol voltage higher or setting the same lower than an intermediatepotential between the two threshold voltages is controlled.

In addition, a PLL circuit according to the present invention comprises:

a phase comparing means for comparing phases between a reference signaland an internal signal and outputting a phase difference signalaccording to a phase difference therebetween;

a plurality of resonant circuits provided with mutually differentresonance frequencies;

an oscillator whose oscillation frequency is controlled in accordancewith the resonant circuits and a phase difference signal;

a selecting means for selecting one of the plurality of resonantcircuits based on the phase difference signal; and

a frequency dividing means for generating the internal signal bydividing an output from the oscillator, wherein

provided is a means for approximating, when the resonant circuitselecting state is changed, an output phase of the frequency dividingmeans to the phase of the reference signal.

In addition, the selecting means switches over the plurality of resonantcircuits based on a history of the phase difference signal or the phasecontrol signal.

In addition, the oscillator is a voltage controlled oscillator, and

-   -   provided is a means for converting the phase difference signal        to an oscillator control voltage.

In addition, provided is a means for setting two threshold voltageshaving mutually different values within a variable voltage range of thecontrol voltage of the voltage controlled oscillator and temporarilysetting a value of the oscillator control voltage in a range between thetwo threshold voltages, when the resonant circuit selecting state ischanged.

In addition, provided is a means for changing a value of the temporarilysetting oscillator control voltage in accordance with a history when theresonant circuit selecting state is changed.

In addition, when the resonant circuit selecting state is switched overas a result of the oscillator control voltage becoming out of the rangebetween the two threshold voltages, the temporarily setting oscillatorcontrol voltage is set, out of the two threshold voltages, in thevicinity of the oscillator control voltage-side threshold voltage.

In addition, when the resonant circuit selecting state is switched overas a result of the oscillator control voltage becoming out of the rangebetween the two threshold voltages and when the oscillator controlvoltage becomes out of the range sandwiched between the two thresholdvoltages twice or more in series, the temporarily setting oscillatorcontrol voltage is set, out of the two threshold voltages, in thevicinity of the oscillator control voltage-side threshold voltage.

In addition, when the oscillator control voltage becomes out of therange between the two threshold voltages, depending on whether thisoscillator control voltage is greater than the two threshold voltages orsmaller than the two threshold voltages, whether setting the oscillatorcontrol voltage higher or setting the same lower than an intermediatepotential between the two threshold voltages is controlled.

In addition, a PLL circuit according to the present invention comprises:

a phase comparing means for comparing phases between a reference signaland an internal signal and outputting a phase difference signalaccording to a phase difference therebetween;

an oscillator constructed by coupling a plurality of delay circuitswhose delay times are respectively controlled in accordance with a phasedifference signal;

a selecting means for switching over the coupling number of delaycircuits based on the phase difference signal; and

a frequency dividing means for generating the internal signal bydividing an output of the oscillator selected by the selecting means,wherein

provided is a means for approximating, when the oscillator selectingstate is changed, an output phase of the frequency dividing means to thephase of the reference signal.

In addition, the selecting means switches over the coupling number ofthe delay circuits based on a history of the phase difference signal orthe phase control signal.

In addition, the oscillator is a voltage controlled oscillator, and

provided is a means for converting the phase difference signal to anoscillator control voltage.

In addition, provided is a means for setting two threshold voltageshaving mutually different values within a variable voltage range of thecontrol voltage of the voltage controlled oscillator and temporarilysetting a value of the oscillator control voltage in a range between thetwo threshold voltages, when the delay circuit coupling number selectingstate is changed.

In addition, provided is a means for changing a value of the temporarilysetting oscillator control voltage in accordance with a history when thedelay circuit coupling number selecting state is changed.

In addition, when the delay circuit coupling number selecting state isswitched over as a result of the oscillator control voltage becoming outof the range between the two threshold voltages, the temporarily settingoscillator control voltage is set, out of the two threshold voltages, inthe vicinity of the oscillator control voltage-side threshold voltage.

In addition, when the delay circuit coupling number selecting state isswitched over as a result of the oscillator control voltage becoming outof the range between the two threshold voltages and when the oscillatorcontrol voltage becomes out of the range between the two thresholdvoltages twice or more in series, the temporarily setting oscillatorcontrol voltage is set, out of the two threshold voltages, in thevicinity of the oscillator control voltage-side threshold voltage.

In addition, when the oscillator control voltage becomes out of therange between the two threshold voltages, depending on whether thisoscillator control voltage is higher than the two threshold voltages orlower than the two threshold voltages, whether setting the oscillatorcontrol voltage higher or setting the same lower than an intermediatepotential between the two threshold voltages is controlled.

In addition, the output phase of the frequency dividing means issynchronized with the phase of the reference signal.

In the present invention constructed as in the above, a PLL circuitcomprises: a phase comparing means for comparing phases between areference signal and an internal signal and outputting a phasedifference signal according to a phase difference therebetween; aplurality of oscillators which have mutually different frequencyvariable ranges and whose frequencies are respectively controlled inaccordance with a phase control signal; a selecting means for selectingone of the outputs from the plurality of oscillators based on the phasedifference signal or the phase control signal; and a frequency dividingmeans for generating the internal signal by dividing an output of theoscillator selected by the selecting means, and when the oscillatorselecting state is changed, an output phase of the frequency divider isapproximated to the phase of the reference signal, therefore, in a PLLcircuit using a plurality of voltage controlled oscillators havingdifferent control voltage-oscillation frequency characteristics, arequired voltage controlled oscillator can be selected according to adesirable oscillation frequency in a short time.

Accordingly, in the present invention, when realizing a broadband PLLcircuit by use of a plurality of voltage controlled oscillators havingdifferent control voltage-oscillation frequency characteristics, arequired voltage controlled oscillator can be automatically selectedaccording to a desirable oscillation frequency in a considerably shorttime, therefore, it becomes possible to avoid, in a system using whileswitching over a plurality of radio methods, causing a considerablyprolonged frequency setting time, thus the invention is preferable forsuch a system.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing a configuration example of a quadruplecircuit to which a first embodiment of a PLL circuit of the presentinvention has been applied.

FIG. 2 is a characteristics diagram showing oscillation frequencycharacteristics, with respect to a voltage of a control signal, of avoltage controlled oscillator group shown in FIG. 1.

FIG. 3 is a block diagram showing a configuration example of a quadruplecircuit to which a second embodiment of a PLL circuit of the presentinvention has been applied.

FIG. 4 is a characteristics diagram showing oscillation frequencycharacteristics, with respect to a voltage of a control signal, of avoltage controlled oscillator group shown in FIG. 3.

FIG. 5 is a characteristics diagram showing oscillation frequencycharacteristics, with respect to a voltage of a control signal, of avoltage controlled oscillator group shown in FIG. 3.

FIG. 6 is a block diagram showing a configuration example of a quadruplecircuit to which a third embodiment of a PLL circuit of the presentinvention has been applied.

FIG. 7 is a block diagram showing a configuration example of a quadruplecircuit to which a fourth embodiment of a PLL circuit of the presentinvention has been applied.

FIG. 8 is a block diagram showing a configuration example of a quadruplecircuit to which a fifth embodiment of a PLL circuit of the presentinvention has been applied.

FIG. 9 is a block diagram showing a configuration example of a quadruplecircuit to which a sixth embodiment of a PLL circuit of the presentinvention has been applied.

FIG. 10 is a diagram showing a configuration example of a quadruplecircuit to select from a plurality of voltage controlled oscillators byan external signal and generate a clock.

FIG. 11 is a block diagram showing a configuration of a selectioncircuit shown in FIG. 10.

FIG. 12 is a characteristics diagram showing oscillation frequencycharacteristics, with respect to a voltage of a control signal, of avoltage controlled oscillator group shown in FIG. 10.

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

FIG. 1 is a block diagram showing a configuration example of a quadruplecircuit to which a first embodiment of a PLL circuit of the presentinvention has been applied. Here, in FIG. 1, identical symbols will beused for components identical to those shown in FIG. 10, whereby adetailed description thereof will be omitted.

As shown in FIG. 1, in the present embodiment, a 2-input AND circuit 7whose first input is a reference signal and whose second input is asignal from a selection circuit 6 is further provided, an outputtherefrom is inputted into a reset terminal of a frequency divider 5,and by this signal, a frequency divider output and the reference signalare synchronized in phase.

In addition, inside the selection circuit 6, a voltage comparator 418having a threshold voltage Vref1 and a voltage comparator 418 having athreshold voltage Vref2 (>Vref1) are provided. In one voltage comparator419, an output signal S15 is set to a high potential (H) for a fixedtime when a voltage of an inputted control signal S4 is lower than thethreshold voltage Vref1, and an output signal S15 is set to a lowpotential (L) for a fixed time when a voltage of an inputted controlsignal S4 is higher than the threshold voltage Vref1. In addition, inthe other voltage comparator 418, an output signal S16 is set to a highpotential (H) for a fixed time when a voltage of an inputted controlsignal S4 is higher than the threshold value Vref2, and an output signalS16 is set to a low potential (L) for a fixed time when a voltage of aninputted control signal S4 is lower than the threshold value Vref2.

The outputs S15 and S16 from the voltage comparators 418 and 419 areinputted into an up/down counter 426, and in accordance with an outputtherefrom, a selection switch 436 is switched over. By the selectioncircuit 6 having such operating characteristics, from fourvoltage-controlled oscillators having different controlvoltage-oscillation frequency characteristics, one voltage controlledoscillator according to a quadruple frequency of a frequency of thereference signal CK1 is automatically selected in accordance with avoltage value of the control signal S4.

Furthermore, when the selecting state is changed by the selectioncircuit 6, a signal S14 temporarily becomes high in potential (H),potential of an output signal S4 from a loop filter 3 is forcibly set toa value higher than the threshold voltage Vref1 shown in FIG. 2 and alsolower than the threshold value Vref2, therefore, outputs from thevoltage comparators 418 and 419 are once returned to a low potential(L). Furthermore, by the 2-input AND circuit 7 into which the signal S14and reference signal are inputted, the frequency divider 5 is reset fora fixed period of time at a point in time of change in the voltagecontrolled oscillator selecting state, whereby, the reference signal andan output phase of the frequency divider 5 are synchronized. Thereby, agreat change in frequency caused by a change in the voltage controlledoscillator selecting state is to be detected by the phase comparator 1in a short time, thus in the selecting state of a voltage controlledoscillator group 4 having different control voltage-oscillationfrequency characteristics, malfunction can be prevented.

As has been described above, in a semiconductor integrated circuitincluding four voltage-controlled oscillators having different controlvoltage-oscillation frequency characteristics, conventionally, only theoutput signal S4 from the loop filter 3 to prevent malfunction whenswitching over voltage controlled oscillators has been forciblycontrolled, however, in the present embodiment, by forciblysynchronizing also an output phase of the frequency divider 5 with thereference signal, it becomes possible to select a preferred voltagecontrolled oscillator in a considerably short time.

FIG. 2 is a characteristics diagram showing oscillation frequencycharacteristics of a voltage controlled oscillator group 4 shown in FIG.1, with respect to a voltage of a control signal S4. Here, A to D arerespectively control voltage-oscillation frequency characteristics offour oscillators, and frequencies f1 to f8 have a relationship off1<f2<f3<f4<f5<f6<f7<f8.

First, description will be given for a case where a desirableoscillation frequency, namely, a quadruple frequency fosc of a frequencyof a reference signal CK1 to be inputted is f1<fosc<f2.

When a lock occurs only at a characteristic D shown in FIG. 2, namely,when voltage of the control signal S4 is not deviated from the rangebetween the threshold voltage Vref1 and threshold voltage Vref2, theoutput signals S15 and S16 from the voltage comparators 418 and 419never become high in potential (H), therefore, the counter 426 neverperforms a counting operation, and the condition of the selectioncircuit 6 does not change from its initial condition.

In addition, when the characteristic shifts from the characteristic D toa characteristic C shown in FIG. 2, further shifts to a characteristicB, and the circuit is finally locked, operations are as follows.

When the control voltage S4 exceeds the threshold voltage Vref2 at thecharacteristic D, the output signal S16 from the voltage comparator 418becomes high in potential (H) for a fixed time, whereby, the counter 426performs an up-counting operation by one. Simultaneously with thevoltage controlled oscillator selecting state shifting from thecharacteristic D to the characteristic C, the signal S14 temporarilybecomes high in potential (H), and the control signal S4 temporarilyreturns to the range between the threshold value Vref1 and thresholdvalue Vref2, therefore, a change in the output signal S16 to a highpotential (H) after switching over the voltage controlled oscillators isprevented.

Furthermore, by the 2-input AND circuit 7 into which the signal S14 andreference signal are inputted, the frequency divider 5 is reset for afixed period of time at a point in time of change in the voltagecontrolled oscillator selecting state, whereby, the reference signal andan output signal of the frequency divider 5 are synchronized in phase,whereby, a great change in frequency caused by a change in the voltagecontrolled oscillator selecting state is detected by a phase comparator1 in a short time, thus in the selecting state of a voltage controlledoscillator group 4 having different control voltage-oscillationfrequency characteristics, malfunction is prevented.

Even after PLL control according to the characteristic C is performed assuch, since frequency of the internal signal is still lower than thequadruple frequency of the reference signal, the control voltage S4again exceeds the threshold voltage Vref2, the selection circuit 6repeats the aforementioned operations, and the characteristic shifts toa characteristic B. At this point in time, the voltage controlledoscillator is outputting a frequency roughly the same as that of thereference signal, while the phase of the frequency divider 5 also has avalue according thereto, therefore, the two frequencies are thereafterequalized, and a lock finally occurs at the characteristic B.

On the other hand, if, for example, the frequency of the referencesignal CK1 is switched over so as to make a desirable oscillationfrequency fosc f1<fosc<f2 in a condition currently being locked to thecharacteristic B, the characteristic switches over, for example, fromthe characteristic B to characteristic C to characteristic D, and thecircuit is finally locked to the characteristic D.

Second Embodiment

FIG. 3 is a block diagram showing a configuration example of a quadruplecircuit to which a second embodiment of a PLL circuit of the presentinvention has been applied. Here, in FIG. 3, identical symbols will beused for components identical to those shown in FIG. 1, whereby adetailed description thereof will be omitted.

As shown in FIG. 3, in the present embodiment, to components shown inthe first embodiment, added is a circuit for storing outputs from thevoltage comparators 418 and 419 in history counters 427 and 428 andchanging, based on the history information stored in the history counter427 and 428, a voltage value to forcibly set an output potential fromthe loop filter 3.

In the present embodiment, when the selecting state is changed by theselection circuit 6, in a case where up or down signals into the up/downcounter 426 are inputted in series, an output value from the loop filter3 is forcibly set, if up signals are consecutive, lower than thethreshold value Vref2 and in the vicinity thereof, and if down signalsare consecutive, higher than the threshold value Vref1 and in thevicinity thereof.

The history counters 427 and 428 are composed of 2-bit shift resisters,respectively, and outputs therefrom are respectively inputted into2-input AND circuit 429 and 430 and 2-input EXOR circuits 431 and 432.

When up signals are inputted twice or more in series, since the uphistory counter 427 outputs, as 2-bit output, the same values, an outputfrom the AND circuit 429 becomes high in potential (H), whereby, anoutput S4 from the loop filter 3 is forcibly set lower than thethreshold value Vref2 and in the vicinity thereof.

When down signals are inputted twice or more in series, since the downhistory counter 428 outputs, as 2-bit output, the same values, an outputfrom the AND circuit 430 becomes high in potential (H), whereby, anoutput S4 from the loop filter 3 is forcibly set higher than thethreshold value Vref1 and in the vicinity thereof.

In addition, when neither up signals nor down signals are inputted twiceor more in series, outputs from the two EXOR circuits 431 and 432 becomehigh in potential (H), and as a result, an output from an OR circuit 433is high in potential (H), and an output from the loop filter 3 is set tothe middle between the threshold values Vref1 and Vref2.

Thereby, even when design is provided with a large number of oscillatorsto cover a wide frequency range, a shifting time from a lowest-frequencycharacteristic to a highest-frequency characteristic can be shortened.

Furthermore, by the 2-input AND circuit 7 into which the signal S14 andreference signal are inputted, the frequency divider 5 is reset for afixed period of time at a period in time of change in the voltagecontrolled oscillator selecting state, whereby the phases of thereference signal and an output of the frequency divider 5 aresynchronized. Thereby, a great change in frequency caused by a change inthe voltage controlled oscillator selecting state is to be detected bythe phase comparator 1 in a short time, thus in the selecting state of avoltage controlled oscillator group 4 having different controlvoltage-oscillation frequency characteristics, malfunction can beprevented.

As has been described above, in a semiconductor integrated circuitincluding four voltage controlled oscillators having different controlvoltage-oscillation frequency characteristics, conventionally, only theoutput signal S4 from the loop filter 3 to prevent malfunction whenswitching over voltage controlled oscillators has been forciblycontrolled. However, in the present embodiment, by adding a circuit forchanging a voltage value to forcibly set an output potential from theloop filter 3, and moreover, by forcibly synchronizing also an outputphase of the frequency divider 5 with that of the reference signal, itbecomes possible to select a preferred voltage controlled oscillator ina considerably short time.

FIG. 4 is a characteristics diagram showing oscillation frequencycharacteristics of a voltage controlled oscillator group 4 shown in FIG.3 with respect to a voltage of a control signal S4. Here, A to D arerespectively control voltage-oscillation frequency characteristics offour oscillators, and frequencies f1 to f8 have a relationship off1<f2<f3<f4<f5<f6<f7<f8.

First, description will be given for a case where a desirableoscillation frequency, namely, a quadruple frequency fosc of a referencesignal CK1 to be inputted is f1<fosc<f2.

When a lock occurs only at a characteristic D shown in FIG. 4, namely,when voltage of the control signal S4 is not deviated from the rangebetween the threshold voltage Vref1 and threshold voltage Vref2, theoutput signals S15 and S16 from the voltage comparators 418 and 419never become high in potential (H), the counter 426 never performs acounting operation, and the condition of the selection circuit does notchange from its initial condition.

In addition, when the characteristic shifts from the characteristic D toa characteristic C shown in FIG. 4, further shifts to a characteristicB, and the circuit is finally locked to a characteristic A, operationsare as follows.

When the control voltage S4 exceeds the threshold voltage Vref2 at thecharacteristic D, the output signal S16 from the voltage comparator 418becomes high in potential (H) for a fixed period of time, whereby, thecounter 426 performs an up-counting operation by one. Simultaneouslywith the oscillator selecting state shifting from the characteristic Dto the characteristic C, the signal S14 temporarily becomes high inpotential (H), and the control signal S4 temporarily returns to therange between the threshold value Vref1 to threshold value Vref2,therefore, a change in the output signal S16 to a high potential (H)after switching over the voltage controlled oscillators is prevented.

Furthermore, by the 2-input AND circuit 7 into which the signal S14 andreference signal are inputted, since the frequency divider 5 is resetfor a fixed period of time at a point in time of change in the voltagecontrolled oscillator selecting state, the phase of the reference signaland an output of the frequency divider 5 are synchronized, a greatchange in frequency caused by a change in the voltage controlledoscillator selecting state is detected by a phase comparator 1 in ashort time, thus in the selecting state of a voltage controlledoscillator group 4 having different control voltage-oscillationfrequency characteristics, malfunction is prevented.

Even after PLL control according to the characteristic C is performed assuch, since frequency of the internal signal is still lower than thequadruple frequency of the reference signal, the control voltage S4again exceeds the threshold voltage Vref2. At this time, since 2-bitoutput from the up history counter 427 simultaneously becomes high inpotential (H), an output from the AND circuit 429 becomes high inpotential (H), whereby, an output S4 from the loop filter 3 is forciblyset lower than the threshold value Vref2 and in the vicinity thereof,and simultaneously, the frequency divider 5 also repeats theaforementioned operations, and the characteristic shifts to thecharacteristic B.

Even after PLL control according to the characteristic B is performed assuch, since frequency of the internal signal is still lower than thequadruple frequency of the reference signal, the control voltage S4again exceeds the threshold voltage Vref2, the selection circuit 6repeats the aforementioned operations, and the characteristic shifts tothe characteristic A.

At this point in time, the voltage controlled oscillator is outputting afrequency roughly the same as that of the reference signal, while thephase of the frequency divider 5 also has a value according thereto,therefore, the two frequencies are thereafter equalized, and a lockfinally occurs at the characteristic A.

On the other hand, if, for example, the frequency of the referencesignal CK1 is switched over so as to make a desirable oscillationfrequency fosc f1<fosc<f2 in a condition currently being locked to thecharacteristic A, the characteristic switches over, for example, fromthe characteristic A to the characteristic B to the characteristic C tothe characteristic D, and the circuit is finally locked to thecharacteristic D.

FIG. 5 is a characteristics diagram showing oscillation frequencycharacteristics of a voltage controlled oscillator group 4 shown in FIG.3 with respect to a voltage of a control signal S4.

As described above, in the present embodiment, the output value S4 fromthe loop filter 3 is set in the vicinity of the threshold voltage Vref1or threshold voltage Vref2, however, this becomes effective when anecessity to greatly change frequency arises. This is because, during ause within an identical band, normally, it is sufficient to finelyadjust frequency in a frequency range of not more than two voltagecontrolled oscillators, however, when jumping to a different band, anecessity to greatly change frequency arises.

Third Embodiment

FIG. 6 is a block diagram showing a configuration example of a quadruplecircuit to which a third embodiment of a PLL circuit of the presentinvention has been applied. Here, in FIG. 6, identical symbols will beused for components identical to those shown in FIG. 1, whereby adetailed description thereof will be omitted.

As shown in FIG. 6, in the present embodiment, for components shown inthe first embodiment, a resonant circuit group 434 composed of aplurality of resonant circuits having different resonance frequencies isprovided in place of voltage controlled oscillators having differentfrequency variable ranges, and by switching over a plurality of resonantcircuits, obtaining effects similar to those shown in the firstembodiment is intended. Here, a resonant circuit is normally composed ofan inductor and a capacitor.

Fourth Embodiment

FIG. 7 is a block diagram showing a configuration example of a quadruplecircuit to which a fourth embodiment of a PLL circuit of the presentinvention has been applied. Here, identical symbols will be used forcomponents identical to those shown in FIG. 1, whereby a detaileddescription thereof will be omitted.

As shown in FIG. 7, in the present embodiment, for components shown inthe second embodiment, a resonant circuit group 434 composed of aplurality of resonant circuits having different resonance frequencies isprovided in place of voltage controlled oscillators having differentfrequency variable ranges, and by switching over a plurality of resonantcircuits, obtaining effects similar to those shown in the secondembodiment is intended. Here, a resonant circuit is normally composed ofan inductor and a capacitor.

Fifth Embodiment

FIG. 8 is a block diagram showing a configuration example of a quadruplecircuit to which a fifth embodiment of a PLL circuit of the presentinvention has been applied. Here, identical symbols will be used forcomponents identical to those shown in FIG. 1, whereby a detaileddescription thereof will be omitted.

As shown in FIG. 8, in the present embodiment, for components shown inthe first embodiment, a ring oscillator 435 to which a plurality ofinverters whose delay times are variable have been connected by couplingis provided in place of voltage controlled oscillators having differentfrequency variable ranges. In the present embodiment, by switching overa coupling number of the ring oscillator 435, frequency can be changedin a wide range.

Sixth Embodiment

FIG. 9 is a block diagram showing a configuration example of a quadruplecircuit to which a sixth embodiment of a PLL circuit of the presentinvention has been applied. Here, identical symbols will be used forcomponents identical to those shown in FIG. 1, whereby a detaileddescription thereof will be omitted.

As shown in FIG. 9, in the present embodiment, for components shown inthe second embodiment, a ring oscillator 435 to which a plurality ofinverters whose delay times are variable have been connected by couplingis provided in place of voltage controlled oscillators having differentfrequency variable ranges. In the present embodiment, by switching overa coupling number of the ring oscillator 435, frequency can be changedin a wide range.

Here, in the aforementioned six embodiments, although description hasbeen given for cases where four voltage controlled oscillators havingdifferent control voltage-oscillation frequency characteristics wereincluded, it is also possible to similarly construct a quadruple circuitfor a case where two or more arbitrary numbers of voltage controlledoscillators are included.

In addition, in the aforementioned embodiments, although voltagecontrolled oscillators having such characteristics that the oscillationfrequency is heightened as the voltage of the control signal S4 becomeshigher in potential, it is also possible to use voltage controlledoscillators having opposite operating characteristics, namely,characteristics that the oscillation frequency is lowered as the voltageof the control signal S4 becomes higher in potential. In this case, ifthe threshold voltages Vref1 and Vref2 are used as they are, thecharacteristic for PLL locking switches over to a characteristic higherin frequency than a current characteristic when the voltage of thesignal S4 becomes less than the threshold voltage Vref1, and it switchesover to a lower-frequency characteristic when the voltage of the signalS4 becomes the threshold voltage Vref2 or more.

In addition, although description has been given of each of the fourvoltage controlled oscillators composing a voltage controlled oscillatorgroup 4 while providing that the threshold voltages Vref1 and Vref2 wereall identical, it can also be considered that the threshold voltagesVref1 and Vref2 are different for each of the four voltage controlledoscillators.

INDUSTRIAL APPLICABILITY

The present invention relates to a PLL circuit which is preferably used,by use of a plurality of voltage controlled oscillators having differentcontrol voltage-oscillation frequency characteristics, for mobilecommunication systems to realize a multiband radio function, namely, atransmitting and receiving function in multiple frequency bands andwhich makes it possible to select, in a short time, a required voltagecontrolled oscillator according to a desirable oscillation frequency.

1. A PLL circuit comprising: a phase comparing means for comparingphases between a reference signal and an internal signal and outputtinga phase difference signal according to a phase difference therebetween;a plurality of oscillators which have mutually different frequencyvariable ranges and whose frequencies are respectively controlled inaccordance with a phase difference signal; a selecting means forselecting one of the outputs from the plurality of oscillators based onthe phase difference signal; and a frequency dividing means forgenerating the internal signal by dividing an oscillator output selectedby the selecting means, wherein provided is a means for approximating,when the oscillator selecting state is changed, an output phase of thefrequency dividing means to the phase of the reference signal.
 2. ThePLL circuit according to claim 1, wherein the plurality of oscillatorshave mutually overlapping frequency variable ranges.
 3. The PLL circuitaccording to claim 1, wherein the plurality of oscillators have mutuallydifferent operating frequency range.
 4. The PLL circuit according toclaim 1, wherein the selecting means switches over outputs from theplurality of oscillators based on a history of the phase differencesignal.
 5. The PLL circuit according to claim 1, wherein the oscillatorsare voltage controlled oscillators, and provided is a means forconverting the phase difference signal to an oscillator control voltage.6. The PLL circuit according to claim 5, wherein provided is a means forsetting two threshold voltages having mutually different values within avariable voltage range of the control voltage of the voltage controlledoscillator and temporarily setting, when the voltage controlledoscillator selecting state is changed, a value of the oscillator controlvoltage in a range between the two threshold voltages.
 7. The PLLcircuit according to claim 6, wherein provided is a means for changing avalue of the temporarily setting oscillator control voltage inaccordance with a history when the voltage controlled oscillatorselecting state is changed.
 8. The PLL circuit according to claim 6,wherein when the voltage controlled oscillator selecting state isswitched over as a result of the oscillator control voltage becoming outof the range between the two threshold voltages, the temporarily settingphase control voltage is set, out of the two threshold voltages, in thevicinity of the oscillator control voltage-side threshold voltage. 9.The PLL circuit according to claim 6, wherein when the voltagecontrolled oscillator selecting state is switched over as a result ofthe oscillator control voltage becoming out of the range between the twothreshold voltages and when the oscillator control voltage becomes outof the range between the two threshold voltages twice or more in series,the temporarily setting oscillator control voltage is set, out of thetwo threshold voltages, in the vicinity of the oscillator controlvoltage-side threshold voltage.
 10. The PLL circuit according to claim6, wherein when the oscillator control voltage becomes out of the rangebetween the two threshold voltages, depending on whether this oscillatorcontrol voltage is higher than the two threshold voltages or lower thanthe two threshold voltages, whether setting the oscillator controlvoltage higher or setting the same lower than an intermediate potentialbetween the two threshold voltages is controlled.
 11. A PLL circuitcomprising: a phase comparing means for comparing phases between areference signal and an internal signal and outputting a phasedifference signal according to a phase difference therebetween; aplurality of resonant circuits provided with mutually differentresonance frequencies; an oscillator whose oscillation frequency iscontrolled in accordance with the resonant circuits and a phasedifference signal; a selecting means for selecting one of the pluralityof resonant circuits based on the phase difference signal; and afrequency dividing means for generating the internal signal by dividingan output from the oscillator, wherein provided is a means forapproximating, when the resonant circuit selecting state is changed, anoutput phase of the frequency dividing means to the phase of thereference signal.
 12. The PLL circuit according to claim 11, wherein theselecting means switches over the plurality of resonant circuits basedon a history of the phase difference signal.
 13. The PLL circuitaccording to claim 11, wherein the oscillator is a voltage controlledoscillator, and provided is a means for converting the phase differencesignal to an oscillator control voltage.
 14. The PLL circuit accordingto claim 13, wherein provided is a means for setting two thresholdvoltages having mutually different values within a variable voltagerange of the control voltage of the voltage controlled oscillator andtemporarily setting, when the resonant circuit selecting state ischanged, a value of the oscillator control voltage in a range betweenthe two threshold voltages.
 15. The PLL circuit according to claim 14,wherein provided is a means for changing a value of the temporarilysetting oscillator control voltage in accordance with a history when theresonant circuit selecting state is changed.
 16. The PLL circuitaccording to claim 14, wherein when the resonant circuit selecting stateis switched over as a result of the oscillator control voltage becomingout of the range between the two threshold voltages, the temporarilysetting oscillator control voltage is set, out of the two thresholdvoltages, in the vicinity of the oscillator control voltage-sidethreshold voltage.
 17. The PLL circuit according to claim 14, whereinwhen the resonant circuit selecting state is switched over as a resultof the oscillator control voltage becoming out of the range between thetwo threshold voltages and when the oscillator control voltage becomesout of the range between the two threshold voltages twice or more inseries, the temporarily setting oscillator control voltage is set, outof the two threshold voltages, in the vicinity of the oscillator controlvoltage-side threshold voltage.
 18. The PLL circuit according to claim14, wherein when the oscillator control voltage becomes out of the rangesandwiched between the two threshold voltages, depending on whether thisoscillator control voltage is greater than the two threshold voltages orsmaller than the two threshold voltages, whether setting the oscillatorcontrol voltage higher or setting the same lower than an intermediatepotential between the two threshold voltages is controlled.
 19. A PLLcircuit comprising: a phase comparing means for comparing phases betweena reference signal and an internal signal and outputting a phasedifference signal according to a phase difference therebetween; anoscillator constructed by coupling a plurality of delay circuits whosedelay times are respectively controlled in accordance with a phasedifference signal; a selecting means for switching over the couplingnumber of delay circuits based on the phase difference signal; and afrequency dividing means for generating the internal signal by dividingan oscillator output selected by the selecting means, wherein providedis a means for approximating, when the oscillator selecting state ischanged, an output phase of the frequency dividing means to the phase ofthe reference signal.
 20. The PLL circuit according to claim 19, whereinthe selecting means switches over the coupling number of the delaycircuits based on a history of the phase difference signal.
 21. The PLLcircuit according to claim 19, wherein the oscillator is a voltagecontrolled oscillator, and provided is a means for converting the phasedifference signal to an oscillator control voltage.
 22. The PLL circuitaccording to claim 21, wherein provided is a means for setting twothreshold voltages having mutually different values within a variablevoltage range of the control voltage of the voltage controlledoscillator and temporarily setting, when the delay circuit couplingnumber selecting state is changed, a value of the oscillator controlvoltage in a range between the two threshold voltages.
 23. The PLLcircuit according to claim 22, wherein provided is a means for changinga value of the temporarily setting oscillator control voltage inaccordance with a history when the delay circuit coupling numberselecting state is changed.
 24. The PLL circuit according to claim 22,wherein when the delay circuit coupling number selecting state isswitched over as a result of the oscillator control voltage becoming outof the range between the two threshold voltages, the temporarily settingoscillator control voltage is set, out of the two threshold voltages, inthe vicinity of the oscillator control voltage-side threshold voltage.25. The PLL circuit according to claim 22, wherein when the delaycircuit coupling number selecting state is switched over as a result ofthe oscillator control voltage becoming out of the range between the twothreshold voltages and when the oscillator control voltage becomes outof the range between the two threshold voltages twice or more in series,the temporarily setting oscillator control voltage is set, out of thetwo threshold voltages, in the vicinity of the oscillator controlvoltage-side threshold voltage.
 26. The PLL circuit according to claim22, wherein when the oscillator control voltage becomes out of the rangebetween the two threshold voltages, depending on whether this oscillatorcontrol voltage is greater than the two threshold voltages or smallerthan the two threshold voltages, whether setting the oscillator controlvoltage higher or setting the same lower than an intermediate potentialbetween the two threshold voltages is controlled.
 27. The PLL circuitaccording to claim 1, wherein the output phase of the frequency dividingmeans is synchronized with the phase of the reference signal.